The Federal Communications Commission (FCC) has allotted a spectrum of bandwidth in the 60 GHz frequency range (57 to 64 GHz). The Wireless Gigabit Alliance (WiGig) is targeting the standardization of this frequency band that will support data transmission rates up to 7 Gbps. Integrated circuits, formed in semiconductor die, offer high frequency operation in this millimeter wavelength range of frequencies. Some of these integrated circuits utilize Complementary Metal Oxide Semiconductor (CMOS), Silicon-Germanium (SiGe) or GaAs (Gallium Arsenide) technology to form the dice in these designs. Since WiGig transceivers use DAC (Digital to Analog Converters), the reduced power supply impacts the performance of the DAC's.
CMOS (Complementary Metal Oxide Semiconductor) is the primary technology used to construct integrated circuits. N-channel transistors and P-channel transistors (MOS transistor) are used in this technology which uses fine line technology to consistently reduce the channel length of the MOS transistors. Current channel lengths examples are 40 nm, the power supply of VDD equals 1.2 V and the number of layers of metal levels can be 8 or more. This technology typically scales with technology.
CMOS technology delivers a designer with the ability to form very large system level design on one die known as a System On a Chip (SOC). The SOC are complex systems with millions, if not billions, of transistors which contain analog circuits and digital circuits. The analog circuits operate purely analog, the digital circuits operate purely digital and these two circuits types can be combined together to form circuits operating in a mixed-signal.
For example, digital circuits in their basic form only use digital logic and some examples can be a component comprising at least one; processor, memory, control logic, digital I/O circuit, reconfigurable logic and/or hardware programmed that to operate as hardware emulator. Analog circuits in their basic form only use only analog circuits and some examples can be a component comprising at least one; amplifier, oscillator, mixer, and/or filter. Mixed signal in their basic form only use both digital and analog circuits and some examples can be a component comprising at least one: DAC (Digital to Analog Convertor), Analog to Digital Converter (ADC), Power Supply control, Phase Lock Loop (PLL), and/or transistor behavior control over Process, Voltage and Temperature (PVT). The combination of digital logic components with analog circuit components can appear to behave like mixed signal circuits; furthermore, these examples that have been provided are not exhaustive as one knowledgeable in the arts understands.
Transceivers comprise at least one transmitter and at least one receiver and are used to interface to other transceivers in a communication system. One version of the transmitter can comprise at least one of each: DAC, LPF (Low Pass Filter), mixer, local oscillator, power amplifier and interface port that are coupled forming a RF (Radio Frequency) transmit chain. One version of the receiver can comprise at least one of each: interface port, LNA (Low Noise Amplifier), mixer, BB (Base Band) amplifier, LPF and ADC that are coupled forming a RF receive chain. Furthermore, each RF transmit and receive chains can operate on an in-phase (I) signal and the quadrature- phase (Q) signal simultaneously.
One of the critical design parameters of a transceiver occurs when a digital signal is converted into an analog signal. As the supply voltage drops to less than 2 times of threshold voltage to reduce leakage and save power, it becomes more and more difficult to provide a relative large swing with a resistor-ladder DAC, since both n-channel MOS transistors and p-channel MOS transistors exhibit large on-resistance to reference voltage close to mid-Vdd, which dramatically increases the settling time and necessitates a large switch size. Also, the mid-Vdd tap itself often has a higher resistance path to supply line, which exacerbates the situation.
When driving an n-channel transistor directly (DC coupling), it is desirable to have a higher reference voltage for the DAC to ensure proper operation of the next stage. The n-channel transistor in a complementary switch becomes more challenging. Nevertheless, p-channel transistor suffers from even higher on-resistance. Simulation shows that even a 10 um/40 nm PMOS shows an on-resistance of approximately 500 Ω when trying to deliver 0.7 V reference voltage with 1.2 V supply.
Such issues have become more serious as the number of bits of the DAC increases. For example, a 5-bit DAC requires 32 switches connected to the same output node, in which situation the combined drain parasitic capacitance of the switches, instead of the input capacitance of the following stage, often dominates the node capacitance. In this case, the settling time of DAC no longer benefits from larger switch sizes. Another solution is required to overcome this problem.